Address Sequencing In Computer Organisation

In computer organisation, address sequencing refers to the method that is used to generate a sequence of memory addresses that the processor follows during the execution of the command. This process is vital because efficient address sequencing is necessary for fast data retrieval. Hence, it is essential for optimal computer performance.

Control memory holds groups of microinstructions where each defines a specific routine. These microinstructions guide the processor in executing tasks by generating the necessary micro-operations. Think of it as a set of detailed instructions that dictate how the computer should carry out operations. 

If the hardware were to manage address sequencing, it would be responsible for navigating between routines and handling the sequencing of microinstructions within each routine.

Now, let’s break down how the instruction code bits are transformed into an address.

To execute a single instruction, the control unit follows these steps:

• First, when the computer powers on, the Control Address Register (CAR) is loaded with an initial address. This address marks the start of the first microinstruction. Using this address, the system triggers the instruction fetch routine.
• Next, the control memory runs the routine to calculate the effective address of the operand.
• Finally, a micro-operation is created to execute the instruction that was fetched from memory. This completes the cycle and enables the operation to take place.

The bits of information can be transformed into an address using the control memory where the routines are stored. This process is known as mapping. Address sequencing plays a key role in the process, and here’s how it works: 

• Based on the status bit conditions, the address sequencing determines whether a conditional or unconditional branch should occur. 
• It can also increment the Control Address Register (CAR), which allows the processor to move through memory addresses.
• Address sequencing facilitates subroutine calls and returns, which lead to smooth execution flow. 
• It maps the instruction bits to specific control memory addresses and guides the system through its operations.

The figure 1 below illustrates a block diagram of control memory and associative hardware that is essential for selecting the address of the next microinstruction. Microinstructions in control memory consist of bits that serve different purposes. Some bits initiate micro-operations in computer registers and other bits determine how the next address is obtained.

The Control Address Register (CAR) retrieves its address through four possible paths. An incrementer updates the CAR and selects the next instruction. Branching addresses are defined within specific microinstruction fields, which allows the system to execute branching efficiently.

Conditional branching is enabled by applying conditions to the status bits of a microinstruction. For external addresses, a mapping logic circuit facilitates sharing. Meanwhile, a dedicated register stores the return address, which is essential when the microprogram needs to exit a subroutine. At that point, the system retrieves the saved address from this special register to resume execution.

In the diagram , the branch logic in the control unit handles decision-making. It uses special status bits that reflect parameters like mode settings, the sign bit, carry-out values, and input or output statuses. These bits provide critical information for controlling how the system behaves.

When combined with the microinstruction field, these status bits help determine the outcome of a conditional branch. The microinstruction field specifies the branch address, and the branch logic hardware, which is implemented using a multiplexer, decides the next step. If the condition is satisfied, the system branches to the specified address. Otherwise, the address register is incremented to proceed sequentially.

An unconditional branch is executed by directly loading a branch address from control memory into the Control Address Register (CAR). For conditional branching, if the condition holds true, the system jumps to the branch address specified in the next address field of the current microinstruction. If the condition fails, the execution will continue without branching. Common conditions tested include zero (Z), carry (C), overflow (O), and negative (N).

In control memory, when a microinstruction specifies a branch to the first word of a routine then a unique type of branch occurs. Each instruction in the system is linked to its corresponding micro-program routine. For this type of branch, the status bits come from the operation code which is part of the instruction.

Figure 2 illustrates a simple mapping process that converts a 4-bit operation code into a 7-bit control memory address. The most significant bit (MSB) of the address is set to 0, which is followed by the 4 bits of the operation code. The two least significant bits (LSBs) of the Control Address Register (CAR) are cleared during the process.

This approach ensures that each computer instruction has an assigned micro-program that is capable of holding up to four microinstructions. If a routine requires fewer than four microinstructions, the unused memory locations can be reassigned to other routines. However, if a routine exceeds four microinstructions then it utilizes memory addresses from 1000000 to 1111111. This system provides flexibility in memory usage while also effectively controlling memory mapping.

This concept can be expanded into a more flexible mapping approach using a Programmable Logic Device (PLD) or Read-Only Memory (ROM). The diagram illustrates how the microinstruction address is derived from the operation code (OP-code) of an instruction. This microinstruction serves as the starting point in the execution sequence that initiates the corresponding routine for the program. Using PLDs or ROMs for mapping ensures a more adaptable method to link operation codes to their respective microinstructions in the control memory.

Subroutines are like mini-programs designed to perform specific tasks that other routines can call upon. Using subroutines helps conserve microinstructions by reusing common sections of microcode, such as those for effective address computation. When the main routine calls a subroutine, the return address is stored in a dedicated subroutine register, which enables the program to resume where it left off after the subroutine finishes. These return addresses are typically stored in a register file, which is often structured as a 'Last In, First Out' (LIFO) stack.

Understanding address sequencing is essential for anyone learning computer architecture, whether you're a student or a professional. It lays the groundwork for optimising data flow, executing instructions, and working on system operations. Mastering this concept strengthens your grasp of how computers work and equips you to design and troubleshoot advanced systems in the future. Whether you're coding, debugging, or developing hardware, a solid understanding of address sequencing will be an asset in your tech toolkit. To learn more, enroll in CCBP 4.0 Academy and prepare for the competitive job market of the future.

1. What is address sequencing in computer organisation?

Address sequencing is the process of generating a sequence of memory addresses to control the execution of instructions in a computer. It enables efficient data retrieval and execution flow by managing how the processor accesses control memory.

2. Why is address sequencing important?

Address sequencing is crucial for optimising system performance. It allows for efficient branching, subroutine management, and instruction execution, all of which are vital for smooth operations in computer systems.

3. How does address sequencing handle branching?

Address sequencing uses status bits and microinstruction fields to determine whether to take a conditional or unconditional branch. The system decides the next address based on these conditions or increments the address register for sequential execution.

4. What role do subroutines play in address sequencing?

Subroutines help reuse common microcode sections and reduce redundancy. They store return addresses in registers which are organized in a LIFO stack. It ensures the program resumes correctly after the subroutine finishes.

5. How does the mapping process work in address sequencing?

Mapping transforms operation code (OP-code) bits into control memory addresses. This process uses logic circuits like PLDs or ROMs to ensure the correct microinstructions are executed based on the instruction's OP code.